MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 519

Manufacturer Part Number

MK30DN512ZVLK10

ARM Microcontrollers - MCU KINETIS 512K SLCD

Manufacturer

Freescale Semiconductor

ARM Cortex M4

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Operating Supply Voltage

1.71 V to 3.6 V

Operating Temperature Range

- 40 C to + 105 C

Package / Case

Mounting Style

Manufacturer

BOSTOCK HK LIMITED

Part Number:

MK30DN512ZVLK10

Manufacturer:

Freescale Semiconductor

Freescale Semiconductor, Inc.

PLL Stop Enable

Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled

even if PLLSTEN =1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL

Clock to run if it is written to 1.

PLL External Reference Divider

Selects the amount to divide down the external reference clock for the PLL. The resulting frequency

must be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN or

PLLS), the PRDIV value must not be changed when LOCK is zero.

MCGPLLCLK is inactive.

MCGPLLCLK is active.

MCGPLLCLK is disabled in any of the Stop modes.

MCGPLLCLK is enabled if system is in Normal Stop mode.

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

MCG_C5 field descriptions (continued)

Table 24-7. PLL External Reference Divide Factor

Chapter 24 Multipurpose Clock Generator (MCG)