MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 450

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map/register definition
21.3.29 TCD Control and Status (DMA_TCD_CSR)
Addresses: 4000_8000h base + 101Ch offset + (32d × n), where n = 0d to 15d
* Notes:
•
450
Reset
Read
Write
MAJORLINKCH
x = Undefined at reset.
Bit
Reserved
15–14
13–12
BWC
11–8
Field
Field
15
x*
BWC
14
x*
else
Bandwidth Control
Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
NOTE: If the source and destination sizes are equal, this field is ignored between the first and second
00
01
10
11
This read-only field is reserved and always has the value zero.
Link Channel Number
If (MAJORELINK = 0) then
else
• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer
• No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted.
DMA_TCDn_DLASTSGA field descriptions (continued)
13
x*
No eDMA engine stalls
Reserved
eDMA engine stalls for 4 cycles after each r/w
eDMA engine stalls for 8 cycles after each r/w
control descriptor to be loaded into this channel. This channel reload is performed as the major
iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a
configuration error is reported.
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
12
x*
DMA_TCDn_CSR field descriptions
11
x*
MAJORLINKCH
Table continues on the next page...
10
x*
x*
9
x*
8
Description
Description
x*
7
x*
6
x*
5
ESG
x*
4
Freescale Semiconductor, Inc.
x*
3
x*
2
x*
1
x*
0