MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 129

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

3.9.2.2 SPI clocking
The SPI module is clocked by the internal bus clock (the DSPI refers to it as system
clock). The module has an internal divider, with a minimum divide is two. So, the SPI
can run at a maximum frequency of bus clock/2.
3.9.2.3 Number of CTARs
SPI CTAR registers define different transfer attribute configurations. The SPI module
supports up to eight CTAR registers. This device supports two CTARs on all instances of
the SPI.
In master mode, the CTAR registers define combinations of transfer attributes, such as
frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In
slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer
attributes.
3.9.2.4 TX FIFO size
3.9.2.5 RX FIFO Size
SPI supports up to 16-bit frame size during reception.
3.9.2.6 Number of PCS signals
The following table shows the number of peripheral chip select signals available per SPI
module.
Freescale Semiconductor, Inc.
SPI Module
SPI Module
SPI0
SPI1
SPI0
SPI1
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 3-61. SPI transmit FIFO size
Table 3-62. SPI receive FIFO size
Transmit FIFO size
Receive FIFO size
4
4
4
4
Chapter 3 Chip Configuration
129