MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 390

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map/register definition
20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
Addresses: 4002_1000h base + 0h offset + (1d × n), where n = 0d to 15d
390
4002_100A
4002_100B
4002_100C
4002_100D
4002_100E
4002_1000
4002_1001
4002_1002
4002_1003
4002_1004
4002_1005
4002_1006
4002_1007
4002_1008
4002_1009
4002_100F
Absolute
address
(hex)
Reset
Read
Write
Bit
Channel Configuration Register (DMAMUX_CHCFG0)
Channel Configuration Register (DMAMUX_CHCFG1)
Channel Configuration Register (DMAMUX_CHCFG2)
Channel Configuration Register (DMAMUX_CHCFG3)
Channel Configuration Register (DMAMUX_CHCFG4)
Channel Configuration Register (DMAMUX_CHCFG5)
Channel Configuration Register (DMAMUX_CHCFG6)
Channel Configuration Register (DMAMUX_CHCFG7)
Channel Configuration Register (DMAMUX_CHCFG8)
Channel Configuration Register (DMAMUX_CHCFG9)
Channel Configuration Register (DMAMUX_CHCFG10)
Channel Configuration Register (DMAMUX_CHCFG11)
Channel Configuration Register (DMAMUX_CHCFG12)
Channel Configuration Register (DMAMUX_CHCFG13)
Channel Configuration Register (DMAMUX_CHCFG14)
Channel Configuration Register (DMAMUX_CHCFG15)
Setting multiple CHCFG registers with the same Source value
will result in unpredictable behavior.
Before changing the trigger or source settings a DMA channel
must be disabled via the CHCFGn[ENBL] bit.
ENBL
7
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
TRIG
0
6
Register name
DMAMUX memory map
0
5
NOTE
NOTE
0
4
0
3
(in bits)
Width
SOURCE
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
2
Freescale Semiconductor, Inc.
Reset value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0
1
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