MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 992

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
The FlexCAN module can store CAN messages for transmission and reception using
Mailboxes and Rx FIFO structures.
This module's memory map includes sixteen 128-bit message buffers (MBs) that occupy
the range from offset 0x80 to 0x17F.
992
4002_401C
4002_402C
4002_404C
4002_4000
4002_4004
4002_4008
4002_4010
4002_4014
4002_4018
4002_4020
4002_4024
4002_4028
4002_4030
4002_4034
4002_4038
4002_4044
4002_4048
Absolute
address
(hex)
Module Configuration Register (CAN0_MCR)
Control 1 Register (CAN0_CTRL1)
Free Running Timer (CAN0_TIMER)
Rx Mailboxes Global Mask Register (CAN0_RXMGMASK)
Rx 14 Mask Register (CAN0_RX14MASK)
Rx 15 Mask Register (CAN0_RX15MASK)
Error Counter (CAN0_ECR)
Error and Status 1 Register (CAN0_ESR1)
Interrupt Masks 2 Register (CAN0_IMASK2)
Interrupt Masks 1 Register (CAN0_IMASK1)
Interrupt Flags 2 Register (CAN0_IFLAG2)
Interrupt Flags 1 Register (CAN0_IFLAG1)
Control 2 Register (CAN0_CTRL2)
Error and Status 2 Register (CAN0_ESR2)
CRC Register (CAN0_CRCR)
Rx FIFO Global Mask Register (CAN0_RXFGMASK)
Rx FIFO Information Register (CAN0_RXFIR)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Register name
Table continues on the next page...
CAN memory map
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Freescale Semiconductor, Inc.
D890_000Fh
00C0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
Undefined
FFFF_
FFFFh
FFFF_
FFFFh
FFFF_
FFFFh
FFFF_
FFFFh
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1002
1003
1004
1005
1005
1007
1011
1012
1012
1013
1015
1019
1020
1020
1021
994
999