MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1059

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in
MCR before executing any other action, otherwise FlexCAN may operate in an
unpredictable way. In Freeze mode, all memory mapped registers are accessible, except
for CTRL1[CLK_SRC] bit that can be read but cannot be written.
Exiting Freeze Mode is done in one of the following ways:
The FRZ_ACK bit is negated after the protocol engine recognizes the negation of the
freeze request. Once out of Freeze Mode, FlexCAN tries to re-synchronize to the CAN
bus by waiting for 11 consecutive recessive bits.
41.4.9.2 Module Disable Mode
This low power mode is normally used to temporarily disable a complete FlexCAN
block, with no power consumption. It is requested by the CPU through the assertion of
the MDIS bit in the MCR Register and the acknowledgement is obtained through the
assertion by the FlexCAN of the LPM_ACK bit in the same register. The CPU must only
consider the FlexCAN in Disable Mode when both request and acknowledgement
conditions are satisfied.
If the module is disabled during Freeze Mode, it requests to disable the clocks to the PE
and CHI sub-modules, sets the LPM_ACK bit and negates the FRZ_ACK bit. If the
module is disabled during transmission or reception, FlexCAN does the following:
Freescale Semiconductor, Inc.
• Grants write access to the Error Counters Register, which is read-only in other modes
• Sets the NOT_RDY and FRZ_ACK bits in MCR
• CPU negates the FRZ bit in the MCR Register
• The MCU is removed from Debug Mode and/or the HALT bit is negated
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of
• Waits for all internal activities like arbitration, matching, move-in and move-out to
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the PE and CHI sub-modules
• Sets the NOTRDY and LPMACK bits in MCR
Intermission and then checks it to be recessive
finish. A pending move-in is not taken into account.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 41 CAN (FlexCAN)
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