MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1399

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

In two-channel mode, both channels (data registers, FIFOs, interrupts and DMA requests)
operate in the same manner, as described above. The only difference is second channel
interrupts are generated only in this mode of operation.
The following figure shows the transmitter and receiver timing for an 8-bit word with
continuous clock, FIFO disabled, three words per frame sync in network mode.
For the receive section, data received on the SRXD pin is transferred to the Rx Data
register at the end of each time slot. If the FIFO is disabled, the ISR[RDR] flag sets and
causes a receiver interrupt if the CR[RE], IER[RIE], and IER[RDREN] bits are set. If the
FIFO is enabled, then the ISR[RFF] flag generates interrupts (this flag is set in
accordance with the watermark settings). In this example all time slots are enabled. The
receive data ready flag is set after reception of the first data (0x55). Because the flag is
not cleared (Rx data register is not read), the receive overrun error (ROE) flag is set on
reception of the next data (0x5E). The ISR[ROE] flag is cleared by writing one to the
corresponding interrupt status bit in I
Freescale Semiconductor, Inc.
• Read RX and use the data.
• Read RX and ignore the data.
• Do nothing—the receiver overrun exception occurs at the end of the current time
slot.
For a continuous clock, the optional frame sync output and
clock output signals are not affected, even if the transmitter or
receiver is disabled. TE and RE do not disable the bit clock or
the frame sync generation. To disable the bit clock and the
frame sync generation, the CR[I2SEN] bit can be cleared, or
CR[TFRCLKDIS]/CR[RFRCLKDIS] bits can be set, or the
port control logic external to the I
The transmitter repeats the value 0x5E because of an underrun
condition
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
2
S status register.
Note
Note
2
S can be reconfigured.
Chapter 46 Integrated interchip sound (I2S)
1399