MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1014

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
Addresses: CAN0_IFLAG1 is 4002_4000h base + 30h offset = 4002_4030h
1014
Reset
Reset
BUF31TO8I
Bit
Bit
W
W
R
R
BUF7I
BUF6I
31–8
Field
7
6
31
15
0
0
30
14
0
0
Buffer MB
Each bit flags the corresponding FlexCAN Message Buffer interrupt.
0
1
Buffer MB7 Interrupt or "Rx FIFO Overflow"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB7.
NOTE: This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF7I flag represents "Rx FIFO Overflow" when MCR[RFEN] is set. In this case, the flag indicates
that a message was lost because the Rx FIFO is full. Note that the flag will not be asserted when the Rx
FIFO is full and the message was captured by a Mailbox.
0
1
Buffer MB6 Interrupt or "Rx FIFO Warning"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB6.
NOTE: This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF6I flag represents "Rx FIFO Warning" when MCR[RFEN] is set. In this case, the flag indicates
when the number of unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
a new one, meaning that the Rx FIFO is almost full. Note that if the flag is cleared while the number of
unread messages is greater than 4, it does not assert again until the number of unread messages within
the Rx FIFO is decreased to be equal to or less than 4.
The corresponding buffer has no occurrence of successfully completed transmission or reception.
The corresponding buffer has successfully completed transmission or reception.
No occurrence of MB7 completing transmission/reception (when MCR[RFEN]=0) or of Rx FIFO
overflow (when MCR[RFEN]=1)
MB7 completed transmission/reception (when MCR[RFEN]=0) or Rx FIFO overflow (when
MCR[RFEN]=1)
29
13
0
0
BUF31TO8I[7:0]
i
Interrupt
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
w1c
27
11
0
0
CANx_IFLAG1 field descriptions
Table continues on the next page...
26
10
0
0
25
0
0
9
BUF31TO8I[bit 8]
24
0
0
8
w1c
Description
w1c
23
0
0
7
w1c
22
0
0
6
w1c
21
0
0
5
20
0
0
4
Freescale Semiconductor, Inc.
19
0
0
3
BUF4TO0I
w1c
18
0
0
2
17
0
0
1
16
0
0
0