MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1090

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory Map/Register Definition
42.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)
PUSHR provides the means to write to the TX FIFO. Data written to this register is
transferred to the TX FIFO. Eight- or sixteen-bit write accesses to the PUSHR transfer all
32 register bits to the TX FIFO. The register structure is different in master and slave
modes. In master mode the register provides 16-bit command and 16-bit data to the TX
FIFO. In slave mode all 32 register bits can be used as data, supporting up to 32-bit SPI
frame operation.
Addresses: SPI0_PUSHR is 4002_C000h base + 34h offset = 4002_C034h
1090
Bit
W
R
Reserved
31
0
CONT
30–28
CTAS
15–0
Field
Field
31
30
0
CTAS
SPI1_PUSHR is 4002_D000h base + 34h offset = 4002_D034h
29
0
28
0
This read-only field is reserved and always has the value zero.
Continuous Peripheral Chip Select Enable
Selects a Continuous Selection Format. The bit is used in SPI master mode. The bit enables the selected
PCS signals to remain asserted between transfers.
0
1
Clock and Transfer Attributes Select.
Selects which CTAR register to use in master mode to specify the transfer attributes for the associated
SPI frame. In SPI slave mode, CTAR0 is used. See the Chip Configuration chapter to determine how
many CTAR registers this device has. You should not program a value in this field for a register that is not
present.
000
001
010
011
100
101
110
111
27
0
Return PCSn signals to their inactive state between transfers.
Keep PCSn signals asserted between transfers.
26
0
CTAR0
CTAR1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
25
0
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
SPIx_RSER field descriptions (continued)
23
0
0
22
0
SPIx_PUSHR field descriptions
21
0
Table continues on the next page...
20
0
PCS[5:0]
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
TXDATA
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
4
0
0
3
0
2
0
1
0
0