MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 723

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

32.7.5 DAC Control Register (CMPx_DACCR)
Addresses: CMP0_DACCR is 4007_3000h base + 4h offset = 4007_3004h
Freescale Semiconductor, Inc.
COUT
Field
CFR
Reset
CFF
Read
IEF
Write
3
2
1
0
Bit
CMP1_DACCR is 4007_3008h base + 4h offset = 4007_300Ch
CMP2_DACCR is 4007_3010h base + 4h offset = 4007_3014h
DACEN
0
1
Comparator Interrupt Enable Falling
The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFF bit is set.
0
1
Analog Comparator Flag Rising
During normal operation, the CFR bit is set when a rising edge on COUT has been detected. The CFR bit
is cleared by writing a logic one to the bit. During Stop modes, CFR can be programmed as either edge or
level sensitive via the SMELB bit.
NOTE: Edge detection during Stop mode is only supported on platforms that allow peripherals to be
0
1
Analog Comparator Flag Falling
During normal operation, the CFF bit is set when a falling edge on COUT has been detected. The CFF bit
is cleared by writing a logic one to the bit. During Stop modes, CFF can be programmed as either edge or
level sensitive via the SMELB bit.
NOTE: Edge detection during Stop mode is only supported on platforms that allow peripherals to be
0
1
Analog Comparator Output
Reading the COUT bit will return the current value of the analog comparator output. The register bit is
reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0).
Writes to this bit are ignored.
7
0
Interrupt disabled.
Interrupt enabled.
Interrupt disabled.
Interrupt enabled.
Rising edge on COUT has not been detected.
Rising edge on COUT has occurred.
Falling edge on COUT has not been detected.
Falling edge on COUT has occurred.
clocked during Stop modes. If the CFR flag is active during Stop mode, then SMELB must be set
to 0 for cases where it is not receiving a clock during Stop mode.
clocked during Stop modes. If the CFF flag is active during Stop mode, then SMELB must be set
to 0 for cases where it is not receiving a clock during Stop mode.
VRSEL
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
CMPx_SCR field descriptions (continued)
0
6
0
5
0
4
Description
0
3
VOSEL
0
2
Chapter 32 Comparator (CMP)
0
1
0
0
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