MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 136

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Communication interfaces
3.9.6.1 Interrupts
The interrupt outputs from the I
interrupt control logic.
3.9.6.2 DMA requests
The I
3.9.6.3 I
To generate the desired frequencies for the I
options as shown below:
These options are controlled by the SIM_SOPT2[I2SSRC] field, and the 8-bit fractional
divider is controlled by the SIM_CLKDIV2[I2SDIV, I2SFRAC] fields. See the
module
136
System memory map
Power management
Signal multiplexing
• Transmit FIFO
• Receive FIFO
• The core/system clock is routed to an 8-bit fractional divider to generate the I
• The PLL output is routed to an 8-bit fractional divider to generate the I
• The EXTAL pin directly drives the I
• The I2S0_CLKIN pin directly drives the I
clock.
2
Clocking
S module has two DMA requests:
Topic
for details.
2
S clock generation
The I2S master clock can be output on the I2S0_MCLK pin or
input on the I2S0_CLKIN pin. Using the I2S0_RX_BCLK pin
to output the I2S master clock in synchronous mode is not
supported on this device.
Table 3-68. Reference links to related information (continued)
Related module
Port control
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
2
S module are OR'd to create a single interrupt to the
2
NOTE
S clock.
2
S module there are multiple clocking
2
S clock.
System memory map
Power management
Signal Multiplexing
Clock Distribution
Reference
Freescale Semiconductor, Inc.
2
S clock.
SIM
2
S