MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 925

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Reset
37.3.2 Timer Load Value Register (PIT_LDVALn)
These registers select the timeout period for the timer interrupts.
Addresses: PIT_LDVAL0 is 4003_7000h base + 100h offset = 4003_7100h
37.3.3 Current Timer Value Register (PIT_CVALn)
These registers indicate the current timer position.
Addresses: PIT_CVAL0 is 4003_7000h base + 104h offset = 4003_7104h
Freescale Semiconductor, Inc.
Bit
Bit
W
W
R
R
31
31
0
0
31–0
31–0
Field
Field
TSV
TVL
30
30
0
0
PIT_LDVAL1 is 4003_7000h base + 110h offset = 4003_7110h
PIT_LDVAL2 is 4003_7000h base + 120h offset = 4003_7120h
PIT_LDVAL3 is 4003_7000h base + 130h offset = 4003_7130h
PIT_CVAL1 is 4003_7000h base + 114h offset = 4003_7114h
PIT_CVAL2 is 4003_7000h base + 124h offset = 4003_7124h
PIT_CVAL3 is 4003_7000h base + 134h offset = 4003_7134h
29
29
0
0
28
28
0
0
Timer Start Value Bits
These bits set the timer start value. The timer will count down until it reaches 0, then it will generate an
interrupt and load this register value again. Writing a new value to this register will not restart the timer,
instead the value will be loaded once the timer expires. To abort the current cycle and start a timer period
with the new value, the timer must be disabled and enabled again.
Current Timer Value
If the timer is enabled, these bits represent the current timer value. If the timer is disabled, do not use this
field as its value is unreliable.
NOTE: The timer uses a downcounter. The timer values are frozen in debug mode if the MCR[FRZ] bit is
27
27
0
0
26
26
0
0
25
25
0
0
set.
24
24
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
23
0
0
22
22
0
0
PIT_LDVALn field descriptions
PIT_CVALn field descriptions
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
16
16
0
0
TSV
TVL
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
Chapter 37 Periodic Interrupt Timer (PIT)
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
925
0
0
0
0