MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1375

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
46.3.9 I
RCR directs the receive operation of the I2S. A power-on reset clears all RCR bits.
However, I2S reset does not affect the RCR bits.
Addresses: I2S0_RCR is 4002_F000h base + 20h offset = 4002_F020h
Freescale Semiconductor, Inc.
Bit
W
R
Reserved
31
0
RXBIT0
RXEXT
RFEN1
RFEN0
RFDIR
31–11
Field
10
30
9
8
7
6
0
29
0
2
28
S Receive Configuration Register (I2Sx_RCR)
0
This read-only field is reserved and always has the value zero.
Receive Data Extension.
This control bit allows I
storage only in case received data is LSB aligned (RCR[9]=1)
0
1
Receive Bit 0.
This control bit allows I
The shifting data direction can be MSB or LSB first, controlled by the RSHFD bit.
0
1
Receive FIFO Enable 1.
This bit enables receive FIFO 1. When enabled, the FIFO allows 15 samples to be received by the I
channel (a 16th sample can be shifting in) before RDR1 bit is set. When the FIFO is disabled, an interrupt
is generated when a single sample is received by the I
0
1
Receive FIFO Enable 0.
This bit enables receive FIFO 0. When enabled, the FIFO allows 15 samples to be received by the I
(per channel) (a 16th sample can be shifting in) before RDR0 bit is set. When the FIFO is disabled, an
interrupt is generated when a single sample is received by the I
0
1
Receive Frame Direction.
27
0
Sign extension turned off.
Sign extension turned on.
Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or
12) of receive shift register (MSB aligned).
Shifting with respect to bit 0 of receive shift register (LSB aligned).
Receive FIFO 1 disabled.
Receive FIFO 1 enabled.
Receive FIFO 0 disabled.
Receive FIFO 0 enabled.
26
0
25
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
22
0
2
2
21
I2Sx_RCR field descriptions
0
0
S to store the received data word in sign extended form. This bit affects data
S to receive the data word at bit position 0 or 15/31 in the receive shift register.
Table continues on the next page...
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
2
S (provided the interrupt is enabled).
12
0
Chapter 46 Integrated interchip sound (I2S)
11
0
2
S (provided the interrupt is enabled).
10
0
1
9
0
8
0
7
0
6
0
5
4
0
0
3
0
2
2
2
S per
S
0
1
1375
0
0