MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1112

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
42.4.7.2 Transmit FIFO Fill Interrupt or DMA Request
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit
FIFO Fill Request is generated when the number of entries in the TX FIFO is less than
the maximum number of possible entries, and the TFFF_RE bit in the RSER is set. The
TFFF_DIRS bit in the RSER selects whether a DMA request or an interrupt request is
generated.
42.4.7.3 Transfer Complete Interrupt Request
The Transfer Complete Request indicates the end of the transfer of a serial frame. The
Transfer Complete Request is generated at the end of each frame transfer when the
TCF_RE bit is set in the RSER.
42.4.7.4 Transmit FIFO Underflow Interrupt Request
The Transmit FIFO Underflow Request indicates that an underflow condition in the TX
FIFO has occurred. The transmit underflow condition is detected only for the DSPI,
operating in slave mode and SPI configuration . The TFUF bit is set when the TX FIFO
of a DSPI is empty, and a transfer is initiated from an external SPI master. If the TFUF
bit is set while the TFUF_RE bit in the RSER is set, an interrupt request is generated.
42.4.7.5 Receive FIFO Drain Interrupt or DMA Request
The Receive FIFO Drain Request indicates that the RX FIFO is not empty. The Receive
FIFO Drain Request is generated when the number of entries in the RX FIFO is not zero,
and the RFDF_RE bit in the RSER is set. The RFDF_DIRS bit in the RSER selects
whether a DMA request or an interrupt request is generated.
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TFFF flag clears automatically when DMA is used to fill
TXFIFO.
To clear TFFF when not using DMA, follow these steps for
every PUSH performed using CPU to fill TXFIFO:
1. Wait until TFFF = 1
2. Write data to PUSHR using CPU.
3. Clear TFFF by writing a 1 to its location. If FIFO is not
full, this flag will not clear.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
NOTE
Freescale Semiconductor, Inc.