MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1324

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Initialization/application of SDHC
The number of blocks left during the data transfer is accessible by reading the contents of
the BLKATTR[BLKCNT] . As the data transfer and the setting of the
PROCTL[SABGREQ] bit are concurrent, and the delay of register read and the register
setting, the actual number of blocks left may not be exactly the value read earlier. The
driver shall read the value of BLKATTR[BLKCNT] after the transfer is paused and the
transfer complete interrupt is received.
It is also possible the last block has begun when the stop at block gap request is sent to
the buffer. In this case, the next block gap is actually the end of the transfer. These types
of requests are ignored and the Driver should treat this as a non-pause transfer and deal
with it as a common write operation.
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10. Set the PROCTL[CREQ] bit to continue the write operation.
11. Wait for the transfer complete interrupt.
12. Check the status bit to see if a write CRC error occurred, or some another error, that
1. Check the card status, wait until card is ready for data.
2. Set the card block length/size:
3. Set the SDHC block length register to be the same as the block length set for the card
4. Set the SDHC number block register (NOB), nob is 5 (for instance).
5. Disable the buffer write ready interrupt, configure the DMA settings and enable the
6. Set the PROCTL[SABGREQ] bit.
7. Wait for the transfer complete interrupt.
8. Clear the PROCTL[SABGREQ] bit.
9. Check the status bit to see if a write CRC error occurred.
in Step 2.
SDHC DMA when sending the command with data transfer. The
XFERTYP[AC12EN] bit should also be set.
occurred during the auto12 command sending and response receiving.
b. For SDIO cards or the I/O portion of SDCombo cards, use
a. For SD/MMC, use SET_BLOCKLEN (CMD16)
c. For CE-ATA cards, configure bits 1~0 in the scrControl register
IO_RW_DIRECT(CMD52) to set the I/O Block Size bit field in the CCCR
register (for function 0) or FBR register (for functions 1~7)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.