MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 441

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
21.3.17 TCD Source Address (DMA_TCD_SADDR)
Addresses: 4000_8000h base + 1000h offset + (32d × n), where n = 0d to 15d
* Notes:
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Freescale Semiconductor, Inc.
Bit
W
R
x = Undefined at reset.
Reserved
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
31
SADDR
CHPRI
31–0
Field
DPA
Field
5–4
3–0
30
6
29
28
0
1
Disable Preempt Ability
0
1
This read-only field is reserved and always has the value zero.
Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled
NOTE: Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number
Source Address
Memory address pointing to the source data.
27
Channel n cannot be suspended by a higher priority channel’s service request
Channel n can be temporarily suspended by the service request of a higher priority channel
Channel n can suspend a lower priority channel
Channel n cannot suspend any channel, regardless of channel priority
26
25
for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
DMA_DCHPRIn field descriptions (continued)
24
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
DMA_TCDn_SADDR field descriptions
22
21
20
19
18
17
SADDR
16
15
Description
Description
14
Chapter 21 Direct Memory Access Controller (eDMA)
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12
11
10
9
8
7
6
5
4
3
2
1
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