MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 543

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

24.5.3.3 Example 3: Moving from BLPI to FEE Mode
In this example, the MCG will move through the proper operational modes from BLPI
mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see
previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz
MCGOUTCLK frequency. First, the code sequence will be described. Then a flowchart
will be included which illustrates the sequence.
Freescale Semiconductor, Inc.
1. First, BLPI must transition to FBI mode.
2. Next, FBI will transition to FEE mode.
b. C1 = 0x10
d. Loop until S[IREFST] is 0, indicating the external reference clock is the current
g. At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and
a. C2 = 0x00
a. C2 = 0x1C
c. Loop until S[OSCINIT] is 1, indicating the crystal selected by the C2[EREFS]
e. Loop until S[CLKST] are 2'b00, indicating that the output of the FLL is selected
f. Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 640,
bit has been initialized.
source for the reference clock.
to feed MCGOUTCLK.
MCGOUTCLK = 31.25 kHz * 640 / 1 = 20 MHz.
C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is
desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL
• C2[LP] is 0
• C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high
• C2[HGO] set to 1 to configure the crystal oscillator for high gain operation.
• C2[EREFS] set to 1, because a crystal is being used.
• C1[CLKS] set to 2'b00 in order to select the output of the FLL as system
• C1[FRDIV] remain at 3'b010, or divide-by-128 for a reference of 4 MHz /
• C1[IREFS] cleared to 0, selecting the external reference clock.
frequency range.
clock source.
128 = 31.25 kHz.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 24 Multipurpose Clock Generator (MCG)
543