MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 518

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
1. A value for FCTRIM is loaded during reset from a factory programmed location .
2. A value for SCFTRIM is loaded during reset from a factory programmed location .
24.3.5 MCG Control 5 Register (MCG_C5)
Address: MCG_C5 is 4006_4000h base + 4h offset = 4006_4004h
518
SCFTRIM
PLLCLKEN
FCTRIM
Reserved
Field
Reset
4–1
Read
Write
Field
0
7
6
Bit
10
11
Fast Internal Reference Clock Trim Setting
FCTRIM
clock period. The FCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0).
Increasing the binary value increases the period, and decreasing the value decreases the period.
If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that
value from the nonvolatile memory location to this register.
Slow Internal Reference Clock Fine Trim
SCFTRIM
SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount
possible.
If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value
from the nonvolatile memory location to this bit.
7
0
0
This read-only field is reserved and always has the value zero.
PLL Clock Enable
Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV
needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4
MHz range prior to setting the PLLCLKEN bit). Setting PLLCLKEN will enable the external oscillator if
not already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN bit, and the
external oscillator is being used as the reference clock, the OSCINIT bit should be checked to make
sure it is set.
Encoding 2 — Mid-high range.
Encoding 3 — High range.
1
controls the fast internal reference clock frequency by controlling the fast internal reference
2
controls the smallest adjustment of the slow internal reference clock frequency. Setting
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
6
MCG_C4 field descriptions (continued)
MCG_C5 field descriptions
Table continues on the next page...
0
5
0
4
Description
Description
0
3
PRDIV
0
2
Freescale Semiconductor, Inc.
0
1
0
0