MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 869

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

36.4.11.3 Boundary Cycle and Loading Points
The boundary cycle definition is important for the loading points for the registers MOD,
CNTIN and C(n)V.
In up counting mode
wraps to its initial value (CNTIN). If in up-down counting mode
then the boundary cycle is defined as when the counter turns from down to up counting
and when from up to down counting.
The following figure shows the boundary cycles and the loading points. In the up
counting mode, the loading points are enabled if one of CNTMIN or CTMAX bits are 1.
In the up-down counting mode, the loading points are selected by CNTMIN and
CNTMAX bits, as indicated in the figure. These loading points are safe places for register
updates thus allowing a smooth transitions in PWM waveform generation.
For both counting modes if neither CNTMIN nor CNTMAX are 1 then the boundary
cycles are not used as loading points for registers updates. See the register
synchronization descriptions in the following sections for details.
Freescale Semiconductor, Inc.
write 1 to SWSYNC bit
write 1 to SWSYNC bit
PWM synchronization
PWM synchronization
software trigger event
software trigger event
system clock
system clock
SWSYNC bit
SWSYNC bit
(Up
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure 36-206. Software Trigger Event
Counting) the boundary cycle is defined as when the counter
selected loading point
(Up-Down
Chapter 36 FlexTimer (FTM)
Counting)
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