MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1096

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
The DSPI is started (DSPI transitions to RUNNING) when all of the following conditions
are true:
The DSPI stops (transitions from RUNNING to STOPPED) after the current frame when
any one of the following conditions exist:
State transitions from RUNNING to STOPPED occur on the next frame boundary if a
transfer is in progress, or immediately if no transfers are in progress.
42.4.2 Serial Peripheral Interface (SPI) Configuration
The SPI Configuration transfers data serially using a shift register and a selection of
programmable transfer attributes. The DSPI is in SPI Configuration when the DCONF
field in the MCR is 0b00. The SPI frames can be 32 bits long. The host CPU or a DMA
controller transfers the SPI data from the external to DSPI RAM queues to a transmit
FIFO (TX FIFO) buffer. The received data is stored in entries in the Receive FIFO (RX
FIFO) buffer. The host CPU or the DMA controller transfers the received data from the
RX FIFO to memory external to the DSPI. The FIFO buffers operation is described in
Transmit First In First Out (TX FIFO) Buffering
Out (RX FIFO) Buffering
described in
The SPI Configuration supports two block-specific modes —master mode and slave
mode. The FIFO operations are similar for both modes. The main difference is that in
master mode the DSPI initiates and controls the transfer according to the fields in the SPI
command field of the TX FIFO entry. In slave mode, the DSPI only responds to transfers
initiated by a bus master external to the DSPI and the SPI command field space is used
for 16 most significant bit of the transmit data.
1096
• SR[EOQF] bit is clear
• MCU is not in the debug mode or the MCR[FRZ] bit is clear
• MCR[HALT] bit is clear
• SR[EOQF] bit is set
• MCU in the debug mode and the MCR[FRZ] bit is set
• MCR[HALT] bit is set
Interrupts/DMA
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Mechanism. The interrupt and DMA request conditions are
Requests.
Mechanism, and
Receive First In First
Freescale Semiconductor, Inc.