MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1034

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
Once the MB is activated in the fourth step, it will participate into the arbitration process
and eventually be transmitted according to its priority. At the end of the successful
transmission, the value of the Free Running Timer is written into the Time Stamp field,
the CODE field in the Control and Status word is updated, the CRC Register is updated, a
status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by
the corresponding Interrupt Mask Register bit. The new CODE field after transmission
depends on the code that was used to activate the MB in step four (see
Table 41-75
When the Abort feature is enabled (MCR[AEN] is asserted), after the Interrupt Flag is
asserted for a MB configured as transmit buffer, the MB is blocked, therefore the CPU is
not able to update it until the Interrupt Flag is negated by CPU. This means that the CPU
must clear the corresponding IFLAG before starting to prepare this MB for a new
transmission or reception.
41.4.2 Arbitration process
The arbitration process scans the Mailboxes searching the Tx one that holds the message
to be sent in the next opportunity. This Mailbox is called the arbitration winner.
The scan starts from the lowest number Mailbox and runs toward the higher ones.
The arbitration process is triggered in the following events:
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3. Write the ID word.
4. Write the data bytes.
5. Write the DLC, Control and CODE fields of the Control and Status word to activate
• From the CRC field of the CAN frame. The start point depends on the
• During the Error Delimiter field of a CAN frame.
• During the Overload Delimiter field of a CAN frame.
• When the winner is inactivated and the CAN bus has still not reached the first bit of
• When there is CPU write to the C/S word of a winner MB and the CAN bus has still
• When CHI is in Idle state and the CPU writes to the C/S word of any MB.
the MB.
CTRL2[TASD] field value.
the Intermission field.
not reached the first bit of the Intermission field.
in Section
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Message Buffer
Structure).
Freescale Semiconductor, Inc.
Table 41-74
and