MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 14

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Section Number
16.2
16.3
17.1
17.2
17.3
17.4
18.1
18.2
14
Memory Map/Register Descriptions.............................................................................................................................325
16.2.1
16.2.2
16.2.3
16.2.4
16.2.5
16.2.6
16.2.7
Functional Description..................................................................................................................................................331
16.3.1
Introduction...................................................................................................................................................................333
17.1.1
Memory Map / Register Definition...............................................................................................................................334
17.2.1
17.2.2
17.2.3
Functional Description..................................................................................................................................................341
17.3.1
17.3.2
17.3.3
Initialization/application information...........................................................................................................................345
Introduction...................................................................................................................................................................347
Overview.......................................................................................................................................................................347
18.2.1
18.2.2
Crossbar switch (AXBS) slave configuration (MCM_PLASC)..................................................................326
Crossbar switch (AXBS) master configuration (MCM_PLAMC)..............................................................326
SRAM arbitration and protection (MCM_SRAMAP).................................................................................327
Interrupt status register (MCM_ISR)...........................................................................................................328
ETB counter control register (MCM_ETBCC)...........................................................................................329
ETB reload register (MCM_ETBRL)..........................................................................................................330
ETB counter value register (MCM_ETBCNT)...........................................................................................331
Interrupts......................................................................................................................................................331
Features........................................................................................................................................................333
Priority Registers Slave (AXBS_PRSn)......................................................................................................335
Control Register (AXBS_CRSn).................................................................................................................338
Master General Purpose Control Register (AXBS_MGPCRn)...................................................................340
General operation.........................................................................................................................................341
Register coherency.......................................................................................................................................342
Arbitration....................................................................................................................................................342
Block Diagram.............................................................................................................................................347
Features........................................................................................................................................................348
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Memory Protection Unit (MPU)
Crossbar Switch (AXBS)
Chapter 17
Chapter 18
Title
Freescale Semiconductor, Inc.
Page

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