MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 29

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Section Number
34.2
34.3
34.4
35.1
35.2
35.3
Freescale Semiconductor, Inc.
Memory Map and Register Definition..........................................................................................................................757
34.2.1
34.2.2
Functional Description..................................................................................................................................................760
34.3.1
34.3.2
Initialization/Application Information..........................................................................................................................761
Introduction...................................................................................................................................................................763
35.1.1
35.1.2
35.1.3
35.1.4
35.1.5
35.1.6
PDB Signal Descriptions..............................................................................................................................................767
Memory Map and Register Definition..........................................................................................................................767
35.3.1
35.3.2
35.3.3
35.3.4
35.3.5
35.3.6
35.3.7
35.3.8
35.3.9
35.3.10
35.3.11
VREF Trim Register (VREF_TRM)............................................................................................................758
VREF Status and Control Register (VREF_SC)..........................................................................................759
Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................760
Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................760
Features........................................................................................................................................................763
Implementation............................................................................................................................................764
Back-to-back Acknowledgement Connections............................................................................................765
DAC External Trigger Input Connections...................................................................................................765
Block Diagram.............................................................................................................................................765
Modes of Operation.....................................................................................................................................767
Status and Control Register (PDBx_SC).....................................................................................................769
Modulus Register (PDBx_MOD).................................................................................................................771
Counter Register (PDBx_CNT)...................................................................................................................772
Interrupt Delay Register (PDBx_IDLY)......................................................................................................772
Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................773
Channel n Status Register (PDBx_CHnS)...................................................................................................774
Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................775
Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................775
DAC Interval Trigger n Control Register (PDBx_DACINTCn).................................................................776
DAC Interval n Register (PDBx_DACINTn)..............................................................................................776
Pulse-Out n Enable Register (PDBx_POEN)...............................................................................................777
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Programmable Delay Block (PDB)
Chapter 35
Title
Page
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