MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1134

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map and Register Descriptions
43.3.10 I2C Address Register 2 (I2Cx_A2)
Addresses: I2C0_A2 is 4006_6000h base + 9h offset = 4006_6009h
1134
SHTF2IE
TCKSEL
SHTF1
SHTF2
SLTF
Field
Reset
Read
Write
4
3
2
1
0
Bit
I2C1_A2 is 4006_7000h base + 9h offset = 4006_7009h
0
1
Timeout counter clock select
Selects the clock source of the timeout counter.
0
1
SCL low timeout flag
This bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-
zero value (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it.
NOTE: The low timeout function is disabled when the SLT register's value is zero.
0
1
SCL high timeout flag 1
This read-only bit sets when SCL and SDA are held high more than clock × LoValue / 512, which
indicates the bus is free. This bit is cleared automatically.
0
1
SCL high timeout flag 2
This bit sets when SCL is held high and SDA is held low more than clock × LoValue/512. Software clears
this bit by writing a 1 to it.
0
1
SHTF2 interrupt enable
Enables SCL high and SDA low timeout interrupt.
0
1
7
1
I2C address register 2 matching is disabled
I2C address register 2 matching is enabled
Timeout counter counts at the frequency of the bus clock / 64
Timeout counter counts at the frequency of the bus clock
No low timeout occurs
Low timeout occurs
No SCL high and SDA high timeout occurs
SCL high and SDA high timeout occurs
No SCL high and SDA low timeout occurs
SCL high and SDA low timeout occurs
SHTF2 interrupt is disabled
SHTF2 interrupt is enabled
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
I2Cx_SMB field descriptions (continued)
1
6
0
5
SAD
0
4
Description
0
3
0
2
Freescale Semiconductor, Inc.
1
1
0
0
0