MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 268

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory map and register definition
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)
The CLKDIV1 register cannot be written to when the device is in VLPR mode.
Address: SIM_CLKDIV1 is 4004_7000h base + 1044h offset = 4004_8044h
* Notes:
•
268
Bit
W
R
x = Undefined at reset.
OUTDIV1
Reserved
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
31
31–28
OUTDIV1
DMA
Field
Field
30
1
0
29
28
DMA Clock Gate Control
This bit controls the clock gate to the DMA module.
0
1
This read-only field is reserved and always has the value zero.
Clock 1 output divider value
This field sets the divide value for the core/system clock. At the end of reset, it is loaded with either 0000
or 0111 depending on FTFL_FOPT[LPBOOT].
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
27
OUTDIV2
Clock disabled
Clock enabled
26
Divide-by-1.
Divide-by-2.
Divide-by-3.
Divide-by-4.
Divide-by-5.
Divide-by-6.
Divide-by-7.
Divide-by-8.
Divide-by-9.
Divide-by-10.
Divide-by-11.
Divide-by-12.
Divide-by-13.
Divide-by-14.
25
24
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
SIM_SCGC7 field descriptions (continued)
23
22
SIM_CLKDIV1 field descriptions
0
21
Table continues on the next page...
20
19
OUTDIV4
18
17
16
15
Description
Description
14
13
12
11
10
9
8
0
Freescale Semiconductor, Inc.
7
6
5
4
3
2
1
0