MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 242

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
During stop mode, the interrupt status flag for any enabled interrupt (but not DMA
request) will asynchronously set if the required level or edge is detected. This also
generates an asynchronous wakeup signal to exit the low power mode.
11.5.4 Digital filter
The digital filter capabilities of the PORT module are available in all digital pin muxing
modes provided the PORT module is enabled.
The clock used for all digital filters within the one port can be configured between the
bus clock or the 1 kHz LPO clock. This selection should be changed only when all digital
filters for that port are disabled. If the digital filters for a port are configured to use the
bus clock, then the digital filters are bypassed (and do not update) during stop mode.
The filter width in clock size is the same for all enabled digital filters within the one port
and should be changed only when all digital filters for that port are disabled.
The output of each digital filter is logic zero after system reset and whenever a digital
filter is disabled. Once a digital filter is enabled, the input is synchronized to the filter
clock (either the bus clock or the 1 kHz LPO clock). If the synchronized input and the
output of the digital filter remain different for a number of filter clock cycles equal to the
filter width register configuration, then the output of the digital filter updates to equal the
synchronized filter input.
The minimum latency through a digital filter equals two or three filter clock cycles plus
the filter width configuration register.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
242
Freescale Semiconductor, Inc.