MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1347

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Chapter 45 Secured digital host controller (SDHC)
45.7.5 (A)DMA address setting
To configure ADMA1/ADMA2/DMA address register, when TC[IRQSTAT] bit is set,
the register will always update itself with the internal address value to support dynamic
address synchronization, so software must make sure TC[IRQSTAT] bit is cleared prior
to configuring ADMA1/ADMA2/DMA address register.
45.7.6 Data port access
Data port does not support parallel access. For example, during an external DMA access,
it is not allowed to write any data to the data port by CPU; or during a CPU read
operation, it is also prohibited to write any data to the data port, by either CPU or external
DMA. Otherwise the data would be corrupted inside the SDHC buffer.
45.7.7 Change clock frequency
SDHC does not automatically gates off the card clock when the host driver changes the
clock frequency. To remove possible glitch on the card clock, clear
SYSCTL[SDCLKEN] bit when changing clock divisor value and set
SYSCTL[SDCLKEN] bit to '1' after PRSSTAT[SDSTB] bit is '1' again.
45.7.8 Multi-block read
For pre-defined multi-block read operation, i.e., the number of blocks to read has been
defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for
SDIO/SDCombo, or whatever multi-block read without abort command at card side, an
abort command, either automatic or manual CMD12/CMD52, is still required by SDHC
after the pre-defined number of blocks are done, to drive the internal start response
timeout. It is recommended to manually send an abort command with
XFERTYP[RSPTYP] both bits cleared.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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