MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 998

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
998
Reserved
Reserved
MAXMB
11–10
IDAM
Field
9–8
6–0
7
frame is sent in the CAN bus without notification. This bit can only be written in Freeze mode as it is
blocked by hardware in other modes.
NOTE: When MCR[AEN] is asserted, only the abort mechanism (see Section "Transmission Abort
CAUTION: Writing the Abort code into Rx Mailboxes can cause unpredictable results when the
0
1
This read-only field is reserved and always has the value zero.
ID Acceptance Mode
This 2-bit field identifies the format of the Rx FIFO ID Filter Table Elements. Note that all elements of the
table are configured at the same time by this field (they are all the same format). See Section "Rx FIFO
Structure". This field can only be written in Freeze mode as it is blocked by hardware in other modes.
00
01
10
11
This read-only field is reserved and always has the value zero.
Number of the Last Message Buffer
This 7-bit field defines the number of the last Message Buffers that will take part in the matching and
arbitration processes. The reset value (0x0F) is equivalent to 16 MB configuration. This field can only be
written in Freeze Mode as it is blocked by hardware in other modes.
Number of the last MB = MAXMB
NOTE: MAXMB must be programmed with a value smaller than the parameter NUMBER_OF_MB,
Additionally, the value of MAXMB must encompass the FIFO size defined by CTRL2[RFFN]. MAXMB also
impacts the definition of the minimum number of peripheral clocks per CAN bit as described in Table
"Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
Matching Timing").
Abort disabled
Abort enabled
Format A: One full ID (standard and extended) per ID Filter Table element.
Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table
element.
Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
Format D: All frames rejected.
Mechanism") must be used for updating Mailboxes configured for transmission.
otherwise the number of the last effective Message Buffer will be: (NUMBER_OF_MB - 1)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
MCR[AEN] is asserted.
CANx_MCR field descriptions (continued)
Description
Freescale Semiconductor, Inc.