MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1053

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

41.4.8.3 Time Stamp
The value of the Free Running Timer is sampled at the beginning of the Identifier field on
the CAN bus, and is stored at the end of "move-in" in the TIME STAMP field, providing
network behavior with respect to time.
Note that the Free Running Timer can be reset upon a specific frame reception, enabling
network time synchronization. Refer to the TSYN description in the description of the
Control 1 Register (CTRL1).
41.4.8.4 Protocol Timing
The following figure shows the structure of the clock generation circuitry that feeds the
CAN Protocol Engine (PE) sub-module. The clock source bit CLKSRC in the CTRL1
Register defines whether the internal clock is connected to the output of a crystal
oscillator (Oscillator Clock) or to the Peripheral Clock (generally from a PLL). In order
to guarantee reliable operation, the clock source should be selected while the module is in
Disable Mode (bit MDIS set in the Module Configuration Register).
The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is
required in the CAN bus timing. The crystal oscillator clock has better jitter performance
than PLL generated clocks.
The FlexCAN module supports a variety of means to setup bit timing parameters that are
required by the CAN protocol. The Control Register has various fields used to control bit
timing parameters: PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW. See the description
of the Control 1 Register (CTRL1).
Freescale Semiconductor, Inc.
• Detection of a dominant bit in the first/second bit of Intermission
• Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames)
• Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload
Frame Delimiter
Peripheral Clock (PLL)
Oscillator Clock (Xtal)
Figure 41-70. CAN Engine Clocking Scheme
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
PE Clock
Prescaler
(1 .. 256)
CLK_SRC
Chapter 41 CAN (FlexCAN)
Sclock
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