MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1129

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
BUSY
RXAK
ARBL
SRW
RAM
IICIF
Field
5
4
3
2
1
0
0
1
Bus busy
Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is
detected and cleared when a STOP signal is detected.
0
1
Arbitration lost
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by
software, by writing a one to it.
0
1
Range address match
This bit is set by any of the following conditions:
Writing the C1 register with any value clears this bit.
0
1
Slave read/write
When addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sent
to the master.
0
1
Interrupt flag
This bit sets when an interrupt is pending. This bit must be cleared by software or by writing a 1 to it in the
interrupt routine. One of the following events can set this bit:
0
1
Receive acknowledge
• Any nonzero calling address is received that matches the address in the RA register.
• The RMEN bit is set and the calling address is within the range of values of the A1 and RA
• One byte transfer including ACK/NACK bit completes if FACK = 0
• One byte transfer excluding ACK/NACK bit completes if FACK = 1. An ACK or NACK is sent on the
• Match of slave address to calling address including primary slave address, range slave address,
• Arbitration lost
• In SMBus mode, any timeouts except SCL and SDA high timeouts
Not addressed
Addressed as a slave
Bus is idle
Bus is busy
Standard bus operation.
Loss of arbitration.
Not addressed
Addressed as a slave
Slave receive, master writing to slave
Slave transmit, master reading from slave
No interrupt pending
Interrupt pending
registers.
bus by writing 0 or 1 to TXAK after this bit is set in receive mode
alert response address, second slave address, or general call address.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
I2Cx_S field descriptions (continued)
Table continues on the next page...
Description
Chapter 43 Inter-Integrated Circuit (I2C)
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