MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1257

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
45.4.9 Buffer Data Port Register (SDHC_DATPORT)
This is a 32-bit data port register used to access the internal buffer and it can not be
updated in idle mode.
Address: SDHC_DATPORT is 400B_1000h base + 20h offset = 400B_1020h
45.4.10 Present State Register (SDHC_PRSSTAT)
The host driver can get status of the SDHC from this 32-bit read only register.
Freescale Semiconductor, Inc.
Bit
W
R
CMDRSP3
DATCONT
31
0
31–0
31–0
Field
Field
30
0
29
0
28
0
The host driver can issue CMD0, CMD12, CMD13 (for
memory) and CMD52 (for SDIO) when the DAT lines are busy
during a data transfer. These commands can be issued when
Command Inhibit (CIHB) is set to zero. Other commands shall
be issued when Command Inhibit (CDIHB) is set to zero.
Possible changes to the SD Physical Specification may add
other commands to this list in the future.
Command Response 3
Data Content
The Buffer Data Port register is for 32-bit data access by the CPU or the external DMA. When the internal
DMA is enabled, any write to this register is ignored, and any read from this register will always yield 0s.
27
0
26
0
25
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
SDHC_CMDRSP3 field descriptions
SDHC_DATPORT field descriptions
22
0
21
0
20
0
19
0
18
0
17
NOTE
0
DATCONT
16
0
15
0
Description
Description
14
0
Chapter 45 Secured digital host controller (SDHC)
13
0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
4
0
0
3
0
2
0
1
1257
0
0