MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 283

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

While in VLPR, the regulator is slow responding and cannot handle fast load transitions.
Therefore, do not change the clock frequency. This includes a requirement to not modify
the module clock enables in the SIM or any clock divider registers.
To re-enter normal run mode, simply clear RUNM. The REGONS and VLPRS bits in the
REGSC register are read-only status bits that indicate if the regulator is in run regulation
mode or not:
VLPR also provides the option to return to run regulation if any interrupt occurs. This is
done by setting the low power wake up on interrupt (LPWUI) bit in the PMCTRL
register. In the interrupt service routine (ISR) it is not be necessary to poll the REGONS
before increasing the frequency. The VLPR frequency limits are such that the regulator is
in run regulation and REGONS is set before the ISR is entered.
Any reset exits VLPR, clears RUNM, REGONS is set, and the device is in normal run
mode after the CPU exits its reset flow.
13.1.2.3 Wait Modes
This device contains two different wait modes:
Freescale Semiconductor, Inc.
• RUNM set to 10b to enter VLPR.
• Flash programming/erasing is not allowed.
• The slow IRC must not be enabled.
• All clock monitors must be disabled before entering VLPR.
• When REGONS is set, the regulator is in run regulation mode and the MCU can run
• When VLPRS is set, the system is fully in VLPR mode.
• Wait
• Very low power wait
at full speed in any clock mode. If a higher execution frequency is desired, poll
REGONS until it is set when returning from VLPR.
• Do not enter VLPS, LLS, or VLLSx until the transition to
• Do not attempt to transition out of run mode until the
VLPR completes as indicated by the VLPRS bit.
REGONS bit sets.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
NOTE
Chapter 13 Mode Controller
283