MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1290

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory map and register definition
45.4.21 ADMA System Address Register (SDHC_ADSADDR)
This register contains the physical system memory address used for ADMA transfers.
Address: SDHC_ADSADDR is 400B_1000h base + 58h offset = 400B_1058h
45.4.22 Vendor Specific Register (SDHC_VENDOR)
This register contains the vendor specific control/status register.
Address: SDHC_VENDOR is 400B_1000h base + C0h offset = 400B_10C0h
1290
Reset
Reset
Bit
W
R
ADSADDR
Bit
Bit
Reserved
W
W
31
0
R
R
31–2
Field
1–0
30
0
31
15
0
0
29
0
28
0
30
14
0
0
ADMA System Address
This register holds the word address of the executing command in the descriptor table. At the start of
ADMA, the host driver shall set the start address of the Descriptor table. The ADMA engine increments
this register address whenever fetching a descriptor command. When the ADMA is stopped at the block
gap, this register indicates the address of the next executable descriptor command. When the ADMA
error interrupt is generated, this register shall hold the valid descriptor address depending on the ADMA
state. The lower 2 bits of this register is tied to ‘0’ so the ADMA address is always word aligned. Since this
register supports dynamic address reflecting, when TC bit is set, it automatically alters the value of
internal address counter, so SW cannot change this register when TC bit is set.
This read-only field is reserved and always has the value zero.
27
0
0
26
0
29
13
0
0
25
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
23
0
SDHC_ADSADDR field descriptions
22
0
27
11
0
0
21
0
20
0
26
10
0
0
19
0
0
18
25
0
0
0
9
ADSADDR
17
0
0
16
24
0
0
0
8
15
0
Description
23
14
0
0
7
0
13
0
22
0
0
12
6
0
11
0
21
0
0
5
10
0
0
9
INTSTVAL
20
0
0
4
0
8
Freescale Semiconductor, Inc.
0
7
19
0
0
3
0
6
0
5
18
0
0
2
4
0
0
3
17
0
0
1
0
2
0
1
16
0
0
1
0
0
0