MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 615

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

1. Must be longword aligned (Flash address [1:0] = 00).
Upon clearing CCIF to launch the Program Check command, the FTFL sets the read
margin for 1s according to
actual read data to the expected data provided by the FCCOB. If the comparison at
margin-1 fails, the MGSTAT0 bit is set.
The FTFL then sets the read margin for 0s, re-reads, and compares again. If the
comparison at margin-0 fails, the MGSTAT0 bit is set. The CCIF flag is set after the
Program Check operation completes.
The supplied address must be longword aligned (the lowest two bits of the byte address
must be 00):
Freescale Semiconductor, Inc.
Command not available in current mode/security
An invalid flash address is supplied
Flash address is not longword aligned
An invalid margin choice is supplied
Either of the margin reads does not match the expected data
Error Condition
Read Margin Choice
• Byte 0 data is expected at the supplied address ('start'),
• Byte 1 data is expected at byte address start + 0b01,
• Byte 2 data is expected at byte address start + 0b10, and
• Byte 3 data is expected at byte address start + 0b11.
FCCOB Number
0x01
0x02
Table 28-33. Program Check Command FCCOB Requirements (continued)
A
B
4
8
9
See the description of margin reads,
Table 28-35. Program Check Command Error Handling
Table 28-34. Margin Level Choices for Program Check
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table
28-34, reads the specified longword, and compares the
Read at 'Factory' margin-1 and 'Factory' margin-0
Read at 'User' margin-1 and 'User' margin-0
NOTE
Margin Level Description
FCCOB Contents [7:0]
Byte 0 expected data
Byte 1 expected data
Byte 2 expected data
Byte 3 expected data
Margin Choice
Margin Read Commands
Chapter 28 Flash Memory Module (FTFL)
FSTAT[MGSTAT0]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
Error Bit
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