MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 853

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0). In this case,
when the counter reaches the value in the CnV register, the CHnF bit is set and the
channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not
modified and controlled by FTM.
36.4.6 Edge-Aligned PWM (EPWM) Mode
The edge-aligned mode is selected when (QUADEN = 0), (DECAPEN = 0), (COMBINE
= 0), (CPWMS = 0), and (MSnB = 1).
The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width
(duty cycle) is determined by (CnV − CNTIN).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (FTM counter = CnV), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM
signals are aligned with the beginning of the period, which is the same for all channels
within an FTM.
Freescale Semiconductor, Inc.
Figure 36-180. Example of the Output Compare Mode when the Match Sets the Channel
channel (n) output
Figure 36-181. EPWM Period and Pulse Width with ELSnB:ELSnA = 1:0
MOD = 0x0005
CnV = 0x0003
It is expected that the output compare mode be used only with
CNTIN = 0x0000.
channel (n) output
counter overflow
CHnF bit
TOF bit
CNT
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
overflow
counter
...
pulse
width
previous value
previous value
period
channel (n) match
0
1
channel (n)
counter overflow
2
match
3
Output
Note
4
overflow
counter
5
0
channel (n) match
1
channel (n)
2
match
counter overflow
3
4
overflow
counter
5
Chapter 36 FlexTimer (FTM)
0
channel (n) match
1
...
853