MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 867

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

36.4.11 PWM Synchronization
The PWM synchronization provides an opportunity to update the MOD, CNTIN, CnV,
OUTMASK, INVCTRL and SWOCTRL registers with their buffered value and force the
FTM counter to the CNTIN register value.
36.4.11.1 Hardware Trigger
Three hardware trigger signal inputs of the FTM module are enabled when TRIGn = 1
(where n = 0, 1 or 2 corresponding to each one of the input signals, respectively). The
hardware trigger input n is synchronized by the system clock. The PWM synchronization
with hardware trigger is initiated when a rising edge is detected at the enabled hardware
trigger inputs.
If (HWTRIGMODE = 0) then the TRIGn bit is cleared when 0 is written to it or when the
trigger n event is detected.
In this case if two or more hardware triggers are enabled (for example, TRIG0 and
TRIG1 = 1) and only trigger 1 event occurs then only TRIG1 bit is cleared. If a trigger n
event occurs together with a write setting TRIGn bit then the synchronization is initiated,
but TRIGn bit remains set due to the write operation.
Freescale Semiconductor, Inc.
• If the selected mode is output compare then CnV register is updated according to the
• If the selected mode is not output compare and (SYNCEN = 1) then CnV register is
SYNCEN bit. If (SYNCEN = 0) then CnV register is updated after CnV register was
written at the next change of the FTM counter (end of the prescaler counting). If
(SYNCEN = 1) then CnV register is updated by the CnV register synchronization
(C(n)V and C(n+1)V Register
updated by the CnV register synchronization
Synchronization).
• It is expected that the PWM synchronization be used only
• The legacy PWM synchronization (SYNCMODE = 0) is a
in combine mode.
subset of the enhanced PWM synchronization
(SYNCMODE = 1). Thus, it is expected that only the
enhanced PWM synchronization be used.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Synchronization).
Note
(C(n)V and C(n+1)V Register
Chapter 36 FlexTimer (FTM)
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