MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 661

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

In some packages, V
externally available, the positive reference(s) may be connected to the same potential as
V
Voltage High and the V
ground references to the same voltage potential as V
31.2.4 Analog channel inputs (ADx)
The ADC module supports up to 24 single-ended analog inputs. A single-ended input is
selected for conversion through the ADCH channel select bits when the DIFF bit in the
SC1n register is low.
31.2.5 Differential analog channel inputs (DADx)
The ADC module supports up to 4 differential analog channel inputs. Each differential
analog input is a pair of external pins (DADPx and DADMx) referenced to each other to
provide the most accurate analog to digital readings. A differential input is selected for
conversion through the ADCH channel select bits when the DIFF bit in the SC1n register
bit is high. All DADPx inputs may be used as single-ended inputs if the DIFF bit is low.
In certain MCU configurations, some DADMx inputs may also be used as single-ended
inputs if the DIFF bit is low. Refer to the Chip Configuration chapter for ADC
connections specific to this MCU.
31.3 Register Definition
This section describes the ADC registers.
Freescale Semiconductor, Inc.
4003_B000
4003_B004
4003_B008
DDA
Absolute
address
(hex)
or may be driven by an external source to a level between the minimum Ref
ADC status and control registers 1 (ADC0_SC1A)
ADC status and control registers 1 (ADC0_SC1B)
ADC configuration register 1 (ADC0_CFG1)
REFH
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
DDA
is connected in the package to V
Register name
potential (V
Table continues on the next page...
ADC memory map
REFH
must never exceed V
SSA
Chapter 31 Analog-to-Digital Converter (ADC)
(in bits)
.
Width
32
32
32
DDA
Access
and V
R/W
R/W
R/W
DDA
REFL
0000_001Fh
0000_001Fh
Reset value
0000_0000h
). Connect the
to V
SSA
Section/
. If
31.3.1/
31.3.1/
31.3.2/
page
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