MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1350

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Introduction
46.1.1 Block diagram
The following figure illustrates the organization of the I
to set up the port, status register, separate transmit and receive circuits with FIFO
registers, and separate serial clock and frame sync generation for the transmit and receive
sections. The second set of Tx and Rx FIFOs replicates the logic used for the first set of
FIFOs.
46.1.2 Features
The I
1350
Peripheral Bus
• Independent (asynchronous) or shared (synchronous) transmit and receive sections
• Normal mode operation using frame sync
with separate or shared internal/external clocks and frame syncs, operating in master
or slave mode.
2
S includes the following features:
32-bit
Transmit Clock
Receive Clock
Control Reg
Control Reg
Transmit
Config Reg
Control Reg
Receive
Config Reg
Figure 46-1. Customer-facing I
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
RCCR
TCR
TCCR
RCR
CR
and shift register logic
Tx and Rx FIFO
Tx and RX
Control
2
S block diagram
Generator
Tx Sync
Generator
Generator
Rx Sync
Generator
Tx Clock
Rx Clock
2
S. It consists of control registers
Freescale Semiconductor, Inc.
SRXD
STXD
STFS
SRCK/SYS_CLK
STCK
SRFS