MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 836

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map and Register Definition
36.3.24 Synchronization Configuration (FTMx_SYNCONF)
This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
and CNTIN registers synchronization, if FTM clears the TRIGj bit (where j = 0, 1, 2)
when the hardware trigger j is detected.
Addresses: FTM0_SYNCONF is 4003_8000h base + 8Ch offset = 4003_808Ch
836
Reset
Reset
HWWRBUF
Bit
Bit
W
W
Reserved
HWINVC
R
R
HWSOC
HWOM
31–21
Field
20
19
18
17
31
15
0
0
FTM1_SYNCONF is 4003_9000h base + 8Ch offset = 4003_908Ch
FTM2_SYNCONF is 400B_8000h base + 8Ch offset = 400B_808Ch
30
14
0
0
0
This read-only field is reserved and always has the value zero.
Software output control synchronization is activated by a hardware trigger.
0
1
Inverting control synchronization is activated by a hardware trigger.
0
1
Output mask synchronization is activated by a hardware trigger.
0
1
MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
0
1
A hardware trigger does not activate the SWOCTRL register synchronization.
A hardware trigger activates the SWOCTRL register synchronization.
A hardware trigger does not activate the INVCTRL register synchronization.
A hardware trigger activates the INVCTRL register synchronization.
A hardware trigger does not activate the OUTMASK register synchronization.
A hardware trigger activates the OUTMASK register synchronization.
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
29
13
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
FTMx_SYNCONF field descriptions
27
11
0
0
Table continues on the next page...
26
10
0
0
0
25
0
0
9
24
0
0
8
Description
23
0
0
7
22
0
0
0
6
21
0
0
5
20
0
0
4
Freescale Semiconductor, Inc.
19
0
0
0
3
18
0
0
2
17
0
0
0
1
16
0
0
0