MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 376

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory map/register definition
Addresses: AIPS0_PACRA is 4000_0000h base + 20h offset = 4000_0020h
376
0x60
0x64
0x68
0x6C
Bit
W
R
Offset
Reserved
31
0
0
WP0
Field
SP0
TP0
31
30
29
28
30
1
AIPS0_PACRB is 4000_0000h base + 24h offset = 4000_0024h
AIPS0_PACRC is 4000_0000h base + 28h offset = 4000_0028h
AIPS0_PACRD is 4000_0000h base + 2Ch offset = 4000_002Ch
AIPS1_PACRA is 4008_0000h base + 20h offset = 4008_0020h
AIPS1_PACRB is 4008_0000h base + 24h offset = 4008_0024h
AIPS1_PACRC is 4008_0000h base + 28h offset = 4008_0028h
AIPS1_PACRD is 4008_0000h base + 2Ch offset = 4008_002Ch
29
0
PACRM
PACRN
PACRO
PACRP
Register
28
0
This read-only field is reserved and always has the value zero.
Supervisor protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
Write protect
Determines whether the peripheral allows write accesss. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0
1
Trusted protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
27
0
0
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
This peripheral allows write accesses.
This peripheral is write protected.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
26
1
PACR96
PACR104
PACR112
PACR120
25
0
[31:28]
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
0
PACR97
PACR105
PACR113
PACR121
22
1
AIPSx_PACRn field descriptions
[27:24]
21
0
Table continues on the next page...
20
0
19
0
0
PACR98
PACR106
PACR114
PACR122
[23:20]
18
1
17
0
16
0
PACR99
PACR107
PACR115
PACR123
[19:16]
15
0
0
Description
14
1
13
0
PACR100
PACR108
PACR116
PACR124
12
0
[15:12]
11
0
0
10
1
PACR101
PACR109
PACR117
PACR125
0
9
[11:8]
0
8
Freescale Semiconductor, Inc.
0
0
7
1
6
PACR102
PACR110
PACR118
PACR126
0
5
[7:4]
4
0
0
0
3
PACR103
PACR111
PACR119
PACR127
1
2
[3:0]
0
1
0
0