MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1033

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

41.4 Functional Description
The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for
transmitting and receiving CAN frames. The mailbox system is composed by a set of up
to 64Message Buffers (MB) that store configuration and control data, time stamp,
message ID and data (see
first 38 MBs can be configured to support a FIFO reception scheme with a powerful ID
filtering mechanism, capable of checking incoming frames against a table of IDs (up to
128 extended IDs or 256 standard IDs or 512 8-bit ID slices), with individual mask
register for up to 32 ID tables. Simultaneous reception through FIFO and mailbox is
supported. For mailbox reception, a matching algorithm makes it possible to store
received frames only into MBs that have the same ID programmed on its ID field. A
masking scheme makes it possible to match the ID programmed on the MB with a range
of IDs on received CAN frames. For transmission, an arbitration algorithm decides the
prioritization of MBs to be transmitted based on the message ID (optionally augmented
by 3 local priority bits) or the MB ordering.
Before proceeding with the functional description, an important concept must be
explained. A Message Buffer is said to be "active" at a given time if it can participate in
both the Matching and Arbitration processes. An Rx MB with a 0b0000 code is inactive
(refer to
(refer to
41.4.1 Transmit Process
In order to transmit a CAN frame, the CPU must prepare a Message Buffer for
transmission by executing the following procedure:
Freescale Semiconductor, Inc.
1. Check if the respective interrupt bit is set and clear it.
2. If the MB is active (transmission pending), write the ABORT code (0b1001) to the
CODE field of the Control and Status word to request an abortion of the
transmission. Wait for the corresponding IFLAG to be asserted by polling the IFLAG
register or by the interrupt request if enabled by the respective IMASK. Then read
back the CODE field to check if the transmission was aborted or transmitted (see
Transmission Abort
bit is negated), just write the INACTIVE code (0b1000) to the CODE field to
inactivate the MB but then the pending frame may be transmitted without notification
(see Section "Message Buffer Inactivation").
Table
Table
41-74). Similarly, a Tx MB with a 0b1000 or 0b1001 code is also inactive
41-75).
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Mechanism). If backwards compatibility is desired (MCR[AEN]
Message Buffer
Structure). The memory corresponding to the
Chapter 41 CAN (FlexCAN)
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