MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 83

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

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3.3.8.5 PACR registers
Each of the two peripheral bridges support up to 128 peripherals each assigned to an
PACRx field within the PACRA-PACRP registers. However, fewer peripherals are
supported on this device. See
the peripheral slot assignments for this device. Unused PACRx fields are reserved.
3.3.8.6 AIPS_Lite PACRE-P register reset values
The AIPSx_PACRE-P reset values depend on if the module is available on your
particular device. For each populated slot in slots 32-127 in
Lite 0) Memory Map
corresponding module's PACR[32:127] field resets to 0x4.
3.3.9 DMA request multiplexer configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Freescale Semiconductor, Inc.
System memory map
Power management
Channel request
Full description
Requests
Clocking
Topic
Figure 3-13. DMA request multiplexer configuration
Table 3-23. Reference links to related information
Related module
DMA controller
and
DMA request
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
multiplexer
Peripheral Bridge 1 (AIPS-Lite 1) Memory
Channel
request
AIPS0 Memory MapandAIPS1 Memory Map
DMA Request
Multiplexer
Peripheral
bridge 0
Register
access
Requests
DMA request sources
System memory map
Power management
Clock distribution
DMA Controller
Reference
DMA Mux
Peripheral Bridge 0 (AIPS-
Module
Module
Module
Chapter 3 Chip Configuration
Map, the
for details of
83

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