MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1310

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
45.5.6.2 Interrupt in 4-bit mode
Since the interrupt and data line 1 share Pin 8 in 4-bit mode, an interrupt will only be sent
by the card and recognized by the host during a specific time. This is known as the
interrupt period. The SDHC will only sample the level on pin 8 during the interrupt
period. At all other times, the host will ignore the level on pin 8, and treat it as the data
signal. The definition of the interrupt period is different for operations with single block
and multiple block data transfers.
In the case of normal single data block transmissions, the interrupt period becomes active
two clock cycles after the completion of a data packet. This interrupt period lasts until
after the card receives the end bit of the next command that has a data block transfer
associated with it.
For multiple block data transfers in 4-bit mode, there is only a limited period of time that
the interrupt period can be active due to the limited period of data line availability
between the multiple blocks of data. This requires a more strict definition of the interrupt
period. For this case, the interrupt period is limited to two clock cycles. This begins two
clocks after the end bit of the previous data block. During this 2-clock cycle interrupt
period, if an interrupt is pending, the SDHC_D1 line will be held low for one clock cycle
with the last clock cycle pulling SDHC_D1 high. On completion of the Interrupt Period,
the card releases the SDHC_D1 line into the high Z state. The SDHC samples the
SDHC_D1] during the interrupt period when the PROCTL[IABG] bit is set.
Refer to SDIO Card Specification v1.10f for further information about the SDIO card
interrupt.
45.5.6.3 Card interrupt handling
When the IRQSIGEN[CINTIEN] bit is set to 0, the SDHC clears the interrupt request to
the host system. The host driver should clear this bit before servicing the SDIO Interrupt
and should set this bit again after all interrupt requests from the card are cleared to
prevent inadvertent interrupts.
The SDIO status bit is cleared by resetting the SDIO interrupt. Writing to this bit would
have no effects. In 1-bit mode, the SDHC will detect the SDIO interrupt with or without
the SD clock (to support wakeup). In 4-bit mode, the interrupt signal is sampled during
the interrupt period, so there are some sample delays between the interrupt signal from
the SDIO card and the interrupt to the host system interrupt controller. When the SDIO
status has been set, and the host driver needs to service this interrupt, so the SDIO bit in
the interrupt control register of SDIO card will be cleared. This is required to clear the
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
1310
Freescale Semiconductor, Inc.