MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1423

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

47.1.3.1 Detailed signal description
47.2 Memory map and register definition
Any read or write access to the GPIO memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states, except
error accesses which complete with one wait state.
Freescale Semiconductor, Inc.
400F_F00C
400F_F000
400F_F004
400F_F008
Absolute
address
(hex)
PORTA[31:0]
PORTB[31:0]
PORTC[31:0]
PORTD[31:0]
PORTE[31:0]
Signal
Port Data Output Register (GPIOA_PDOR)
Port Set Output Register (GPIOA_PSOR)
Port Clear Output Register (GPIOA_PCOR)
Port Toggle Output Register (GPIOA_PTOR)
Table 47-2. GPIO interface-detailed signal descriptions
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Register name
Table continues on the next page...
I/O
I/O
GPIO memory map
State meaning
Chapter 47 General purpose input/output (GPIO)
Timing
(in bits)
Width
General purpose input/output.
32
32
32
32
Access
(always
(always
(always
Description
reads
reads
zero)
zero)
R/W
W
W
W
Asserted - pin is logic one.
Negated - pin is logic zero.
Assertion - when output,
occurs on rising edge of the
system clock. For input, may
occur at any time and input
may be asserted
asynchronously to the system
clock.
Negation - when output,
occurs on rising edge of the
system clock. For input, may
occur at any time and input
may be asserted
asynchronously to the system
clock.
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
Section/
47.2.1/
47.2.2/
47.2.3/
47.2.4/
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