MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1269

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

45.4.13 Interrupt Status Register (SDHC_IRQSTAT)
An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least
one of the status bits is set to 1. For all bits, writing 1 to a bit clears it; writing to 0 keeps
the bit unchanged. More than one status can be cleared with a single register write. For
Card Interrupt, before writing 1 to clear, it is required that the card stops asserting the
interrupt, meaning that when the Card Driver services the interrupt condition, otherwise
the CINT bit will be asserted again.
Freescale Semiconductor, Inc.
HCKEN
IPGEN
Field
1
0
0b
1b
System Clock Enable
If this bit is set, system clock will always be active and no automatic gating is applied. When this bit is
cleared,
system clock
will be automatically off when no data transfer is on the SD bus.
0b
1b
IPG Clock Enable
If this bit is set, bus clock will always be active and no automatic gating is applied.
The bus clock will be internally gated off, if none of the following factors are met:
NOTE: The bus clock will not be auto gated off if the SDHC clock is not gated off. So clearing only this
0b
1b
• Continue request is just set, or
• This bit is set, or
• Card insertion is detected, or
• Card removal is detected, or
• Card external interrupt is detected, or
• 80 clocks for initialization phase is ongoing
• The cmd part is reset, or
• Data part is reset, or
• Soft reset, or
• The cmd is about to send, or
• Clock divisor is just updated, or
• Continue request is just set, or
• This bit is set, or
• Card insertion is detected, or
• Card removal is detected, or
• Card external interrupt is detected, or
• The SDHC clock is not gated off
SDHC clock will be internally gated off
SDHC clock will not be automatically gated off
System clock will be internally gated off
System clock will not be automatically gated off
Bus clock will be internally gated off
Bus clock will not be automatically gated off
bit has no effect unless the PEREN bit is also cleared.
SDHC_SYSCTL field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Description
Chapter 45 Secured digital host controller (SDHC)
1269