MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1477

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
49.3.7 LCD waveform register (LCD_WF3TO0)
The WFyTOx registers each contain four waveform control (WFn) fields, where x is the
n index value of the WFn field in the least-significant byte (bits 7-0) and y is the n index
value of the WFn field in the most-significant byte (bits 31-24). The bits in each WFn
field control the frontplane segments or backplane phases connected to the LCD_Pn
signal.
In an LCD controller, each element consists of a frontplane segment and a backplane
phase. These segments and phases are labeled A through H (x8 multiplexing, 1/8 duty
cycle). Each LCD_Pn signal can be connected to one or more segments (in frontplane
operation) or one or more phases (in backplane operation). An LCD element is turned on
when the associated backplane phase is activated and the frontplane segment is on.
If LCD_Pn is configured for frontplane operation, the bits in WFn turn on or off each of
the frontplane segments connected to LCD_Pn: bit 0 controls segment A, bit 1 controls
segment B, and so on.
If LCD_Pn is configured for backplane operation, the bits in WFn activate or deactivate
each of the backplane phases connected to LCD_Pn: bit 0 controls phase A, bit 1 controls
phase B, and so on.
Software can write to this register with 8-bit, 16-bit, or 32-bit writes. After reset, the
WFyTOx register is cleared to 0.
Address: LCD_WF3TO0 is 400B_E000h base + 20h offset = 400B_E020h
Freescale Semiconductor, Inc.
Bit
W
R
31
0
31–24
Field
WF3
30
0
29
0
28
0
WF3
The reset value of this register depends on the reset type:
Segment-on frontplane operation — Each bit turns on or off the segments associated with LCD_P3 in
the following pattern: HGFEDCBA (most-significant bit controls segment H and least significant bit
controls segment A).
Segment-on backplane operation — Each bit activates or deactivates the phases associated with
LCD_P3 in the following pattern: HGFEDCBA (most-significant bit controls phase H and least significant
bit controls phase A).
27
0
• POR -- 0x0000_0000
26
0
25
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
22
0
LCD_WF3TO0 field descriptions
21
0
Table continues on the next page...
20
0
WF2
19
0
18
0
NOTE
17
0
16
0
15
0
Description
14
0
13
0
12
0
WF1
11
0
10
0
0
9
Chapter 49 LCD Controller (SLCD)
0
8
0
7
0
6
0
5
4
0
WF0
0
3
0
2
0
1
1477
0
0