MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 462

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
Assuming zero wait states on the system bus, DMA requests can be processed every 9
cycles. Assuming an average of the access times associated with internal peripheral bus-
to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can
be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle ?
+5. The resulting peak request rate, as a function of the system frequency, is shown in the
following table.
A general formula to compute the peak request rate with overlapping requests is:
where:
462
16
PEAKreq
freq
entry
read_ws
write_ws
exit
With internal peripheral
bus read and internal
PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ]
SRAM write
Table 21-294. Hardware service request process, cycles 8–17 (continued)
System frequency (MHz)
100.0
133.3
150.0
66.6
83.3
Table 21-295. eDMA peak request rate (MReq/sec)
Where
Cycle
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
17
Table 21-296. Peak request formula legend
internal peripheral bus
With SRAM read and
write
with zero wait states
Request rate
The next channel to be activated performs the read of the
first part of its TCD from the local memory. This is equivalent
to Cycle 4 for the first channel's service request.
Peak request rate
System frequency
Channel startup (4 cycles)
Wait states seen during the system bus read data phase
Wait states seen during the system bus write data phase
Channel shutdown (3 cycles)
11.1
14.8
16.6
7.4
9.2
Description
Represents
Freescale Semiconductor, Inc.
with wait states
Request rate
11.6
13.0
5.8
7.2
8.7