MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1061

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

In the Self Wake mechanism, if the SLF_WAK bit in MCR Register was set at the time
FlexCAN entered Doze Mode, then upon detection of a recessive to dominant transition
on the CAN bus, FlexCAN negates the DOZE bit, requests to resume its clocks and
negates the LPM_ACK after the CAN protocol engine recognizes the negation of the
Doze Mode request. It also sets the WAK_INT bit in the ESR Register and, if enabled by
the WAK_MSK bit in MCR, generates a Wake Up interrupt to the CPU. FlexCAN will
then wait for 11 consecutive recessive bits to synchronize to the CAN bus. As a
consequence, it will not receive the frame that woke it up. The following table details the
effect of SLF_WAK and WAK_MSK upon wake-up from Doze Mode.
41.4.9.4 Stop Mode
This is a system low power mode in which all MCU clocks can be stopped for maximum
power savings. The Stop Mode is globally requested by the CPU and the
acknowledgement is obtained through the assertion by the FlexCAN of a Stop
Acknowledgement signal. The CPU must only consider the FlexCAN in Stop Mode
when both request and acknowledgement conditions are satisfied.
If FlexCAN receives the global Stop Mode request during Freeze Mode, it sets the
LPM_ACK bit, negates the FRZ_ACK bit and then sends the Stop Acknowledge signal
to the CPU, in order to shut down the clocks globally. If Stop Mode is requested during
transmission or reception, FlexCAN does the following:
Freescale Semiconductor, Inc.
• CPU removing the Doze Mode request
• CPU negating the DOZE bit of the MCR Register
• Self Wake mechanism
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of
Intermission and checks it to be recessive
SLF_WAK
0
0
1
1
1
1
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
WAK_INT
Table 41-86. Wake-up from Doze Mode
0
0
1
1
-
-
WAK_MSK
0
1
0
1
-
-
FlexCAN Clocks
Enabled
Yes
Yes
No
No
No
No
Chapter 41 CAN (FlexCAN)
Wake-up Interrupt
Generated
Yes
No
No
No
No
No
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