MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 664

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Register Definition
31.3.1 ADC status and control registers 1 (ADCx_SC1n)
The SC1A register is used for both software and hardware trigger modes of operation.
To allow sequential conversions of the ADC to be triggered by internal peripherals, the
ADC can have more then one status and control register: one for each conversion. The
SC1B-SC1n registers indicate potentially multiple SC1 registers for use only in hardware
trigger mode. Refer to the Chip Configuration information about the number of SC1n
registers specific to this device. The SC1n registers have identical fields, and are used in
a "ping-pong" approach to control ADC operation.
At any one point in time, only one of the SC1n registers is actively controlling ADC
conversions. Updating SC1A while SC1n is actively controlling a conversion is allowed
(and vice-versa for any of the SC1n registers specific to this MCU).
664
400B_B03C
400B_B04C
400B_B05C
400B_B06C
400B_B040
400B_B044
400B_B048
400B_B050
400B_B054
400B_B058
400B_B060
400B_B064
400B_B068
Absolute
address
(hex)
ADC plus-side general calibration value register
(ADC1_CLP4)
ADC plus-side general calibration value register
(ADC1_CLP3)
ADC plus-side general calibration value register
(ADC1_CLP2)
ADC plus-side general calibration value register
(ADC1_CLP1)
ADC plus-side general calibration value register
(ADC1_CLP0)
ADC PGA register (ADC1_PGA)
ADC minus-side general calibration value register
(ADC1_CLMD)
ADC minus-side general calibration value register
(ADC1_CLMS)
ADC minus-side general calibration value register
(ADC1_CLM4)
ADC minus-side general calibration value register
(ADC1_CLM3)
ADC minus-side general calibration value register
(ADC1_CLM2)
ADC minus-side general calibration value register
(ADC1_CLM1)
ADC minus-side general calibration value register
(ADC1_CLM0)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Register name
ADC memory map (continued)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Freescale Semiconductor, Inc.
0000_000Ah
Reset value
0000_0200h
0000_0100h
0000_0080h
0000_0040h
0000_0020h
0000_0000h
0000_0020h
0000_0200h
0000_0100h
0000_0080h
0000_0040h
0000_0020h
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