MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 279

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

13.1.2.1 Power Mode Transitions
The following shows the power mode state transitions available on the device.
Freescale Semiconductor, Inc.
VLPR
VLPW
VLPS
LLS
VLLS3
VLLS2
VLLS1
Mode
The Core Clock, System Clock and Bus Clocks maximum frequency is restricted to 2MHz max,
Flash Clock is restricted to 1MHz. The slow IRC within the MCG must not be enabled when VLPR
is entered.
In ARM architectures, the Core Clock to the ARM Cortex-M4 core is shut off. The System Clock
continues to operate; Bus Clocks if enabled continue to operate; System and Bus clock restricted to
2MHz max, Flash Clock is restricted to 1MHz
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid.
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock and Bus Clocks are stopped after all stop acknowledge signals from
supporting peripherals are valid. MCU is placed in a low leakage mode by reducing the voltage to
internal logic. Internal logic states are retained.
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering
down the internal logic. System RAM contents retained and I/O states held. Internal logic states are
not retained.
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering
down the internal logic and part of system RAM. The rest of the system RAM contents are retained
and I/O states held. Internal logic states are not retained.
NOTE: See the device's Chip Configuration details for the amount of SRAM retained in VLLS2
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering
down the internal logic and all system RAM. A 32-byte register file (available in all modes) contents
retained and I/O states held. Internal logic states are not retained.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
mode.
Table 13-1. Power modes (continued)
Description
Chapter 13 Mode Controller
279